The present invention relates to a signal processing method and a device for implementing the signal processing method. Specifically, the present invention relates to a block-based coding method which requires a higher processing speed and a device for implementing the coding method.
The field of image compression includes image coding techniques, such as MPEG, JPEG, etc. These coding techniques are image compression techniques wherein an image is divided into a plurality of blocks and sequentially encoded based on a block-by-block basis. The still image coding techniques, represented by JPEG, employ intraframe predictive coding (hereinafter, “intra coding”) wherein the spatial redundancy in this small region (block) is utilized for achieving reduction in the amount of information (compression). The motion picture coding techniques, represented by MPEG, employ, in addition to the intra coding, interframe predictive coding (hereinafter, “inter coding”) wherein the amount of information is reduced by using temporal prediction, for the purpose of meeting a demand for compressing a larger amount of information than the still image compression.
Hereinafter, the processes commonly performed in these coding techniques are briefly described with reference to FIG. 22. In the first place, image data divided into blocks is subjected to discrete cosine transformation (hereinafter, “DCT”) in an orthogonal transformer. Then, for the purpose of increasing the coding efficiency (compression efficiency) by removing a high frequency component which is difficult for a human eye to visually perceive, DCT coefficients are quantized by a quantizer to obtain quantized DCT coefficients. These quantized DCT coefficients are temporarily stored in a storage unit in the write order called “raster scan”. The quantized DCT coefficients temporarily stored in the storage unit are then read in the read order called “zigzag scan” and sequentially Huffman-coded by an encoder. Since the order of generating the quantized DCT coefficients and the order of coding the quantized DCT coefficients are different in the block-based coding process, the storage unit is indispensable for carrying out rearrangement of data (change of the scan mode).
In order to increase the processing speed in the above coding process, the speed of controlling memory write and read processes is increased. Such a technique has been known as disclosed in, for example, Japanese Unexamined Patent Publication No. 11-252338 (FIGS. 9 to 11). The technique disclosed in this publication is specifically described below.
A signal processing device 1001 of FIG. 23 is an example of a typical signal processing device disclosed in the above publication. This device is capable of performing the above-described rearrangement of data with high speed. FIG. 24A shows a write scan (raster scan) in a storage unit. FIG. 24B shows a read scan (zigzag scan) from the storage unit.
The signal processing device 1001 of FIG. 23 includes input terminals 2 and 3, input selectors 4 and 5, a storage unit 7, output selectors 9 and 10, output terminals 11 and 12, and a memory control circuit 8. Through the input terminals 2 and 3, n pieces of data which are consecutive in the write scan (first scan) order are sequentially input (herein, n=2). In this example, the data are quantized DCT coefficients (hereinafter, simply referred to as “coefficients”). The input selectors 4 and 5 sort the coefficients input through the input terminals 2 and 3 into a plurality of memories. The storage unit 7 includes a first memory 701 and a second memory 702 for temporarily storing the coefficients. The output selectors 9 and 10 each select one of the n coefficients read from the storage unit 7 (herein, n=2). The coefficients selected by the output selectors 9 and 10 are output through the output terminals 11 and 12, respectively. The memory control circuit 8 controls writing/reading of data in/from the storage unit 7.
High speed data rearrangement with the signal processing device 1001 having the above-described structure is described below.
<Write Control>
Two coefficients input through the input terminals 2 and 3 are input to the input selectors 4 and 5. The first input selector 4 selects a coefficient to be written in the first memory 701, from among the coefficients input through the input terminals 2 and 3 in parallel, based on selection signal S1 input from the memory control circuit 8. The first input selector 4 outputs the selected coefficient as write data WD 1 which is data to be written in the first memory 701. In the meantime, the second input selector 5 selects a coefficient to be written in the second memory 702, from among the coefficients input through the input terminals 2 and 3 in parallel, based on selection signal S2 input from the memory control circuit 8. The second input selector 5 outputs the selected coefficient as write data WD2 which is data to be written in the second memory 702.
Herein, selection signals S1 and S2 are generated such that the coefficients which are consecutive in the write scan order are alternately sorted into the first memory 701 and the second memory 702 on a one-by-one basis, for the purpose of sequentially reading the coefficients from the first memory 701 and the second memory 702 in parallel in the read scan order on a two-by-two basis.
The first memory 701 sequentially writes write data WD1 supplied from the first input selector 4 in address A1 according to address A1 and write enable signal WE1 which are supplied from the memory control circuit 8. The second memory 702 sequentially writes write data WD2 supplied from the second input selector 5 in address A2 according to address A2 and write enable signal WE2 which are supplied from the memory control circuit 8.
FIGS. 25A and 25B show an example of a memory map where the coefficients are sorted into the first memory 701 and the second memory 702 under the above-described control. FIG. 26A shows a specific example of addressing in a write operation in the first memory 701 and the second memory 702 having such a memory map.
<Read Control>
Next, control of sequentially reading quantized DCT coefficients in the read scan order on a two-by-two basis in parallel is described.
In the first place, the memory control circuit 8 sequentially supplies addresses A1 and A2 shown in FIG. 26B to the first memory 701 and the second memory 702 such that the coefficients sorted into the first memory 701 and the second memory 702 under the above-described write control are read from each memory on a one-by-one basis in parallel. In the meantime, the memory control circuit 8 supplies read enable signals RE1 and RE2 to the first memory 701 and the second memory 702, respectively. As a result, the first memory 701 sequentially outputs the quantized DCT coefficients as RD1 in the order of 0, 16, 9, 10, . . . , 47, and 63. On the other hand, the second memory 702 sequentially outputs the quantized DCT coefficients as RD2 in the order of 1, 8, 2, 3, . . . and 62.
The two coefficients, i.e., RD1 and RD2, which have been read on a one-by-one basis, are input to the output selectors 9 and 10. The memory control circuit 8 supplies selection signals S4 and S5 to the output selectors 9 and 10, respectively, such that a former one of the two coefficients in the read scan (second scan) order is output to the output terminal 11 while the other (latter) coefficient is output to the output terminal 12.
That is, the quantized DCT coefficients are output to the output terminal 11 in the order of 0, 8, 9, 3, . . . , 62 and to the output terminal 12 in the order of 1, 16, 2, 10, . . . 63. Under such control, rearrangement of the coefficients is performed with high speed.
As described above, the storage unit is formed by n memories, and data which are consecutive in the write scan (first scan) order are sorted in advance into the n different memories in a data write operation such that n consecutive pieces of data are simultaneously output from the different memories in the read scan order. With such a structure, parallel reading of data is possible, and therefore, high speed coding is achieved.
In the case where the available read scan (second scan) mode is only the zigzag scan as in JPEG coding, change of the scan mode with high speed can be achieved by using the above-described technique. However, the above-described technique is not applicable to the case where a plurality of read scan modes (e.g., alternate horizontal scan, alternate vertical scan, zigzag scan) are available as in MPEG-4 which is an image compression technique used for achieving low bit rate coding of motion pictures.
In recent years, MPEG-4, which achieves low bit rate coding, has been applied to various devices, such as cellular phone systems, etc. It is obviously expected that demands for coding of higher resolution images and coding with higher frame rate increase along with the advances of broadband environments in the future.
MPEG-4 has introduced various new techniques for achieving low bit rate, including predictive coding which is employed for the purpose of improving the coding efficiency in an intraframe predictive coding (intra coding) process.
In MPEG-4, in order to improve the coding efficiency in intra coding, an optimum prediction block is selected from a plurality of blocks adjacent to a block to be coded (target block), and the difference between the selected prediction block and the target block is coded in a sequential manner. This coding process is described with reference to FIG. 27.
In FIG. 27, block X is a block to be coded (target block), and blocks A, B and C are adjacent to block X. Blocks X, A, B and C each include a plurality of DCT coefficients.
Prediction block P of block X is selected as shown in Expression (1):if (|σA−σB|<|σB−σC|)  [Expression (1)]                P=C else        P=A,where σA is a DC coefficient of block A,        σB is a DC coefficient of block B,        σC is a DC coefficient of block C, and        |z| is the absolute value of z.The gradients of the DC coefficients of adjacent blocks A, B and C are calculated, and a block having the larger gradient is selected as prediction block P of block X.        
For example, when block C is selected as prediction block P based on Expression (1), the difference between block X and block C is coded. Alternatively, when block A is selected as prediction block P, the difference between block X and block A is coded (coefficient predictive coding).
Further, MPEG-4 supports two types of prediction methods as the coefficient prediction coding, i.e., DC predictive coding and DC/AC predictive coding.
In the DC prediction coding, only the DC coefficient among the coefficients of the thus-selected prediction block is predicted. The read scan mode for coefficients in a coding process is fixed to zigzag scan (second scan).
The DC/AC predictive coding intends to achieve higher coding efficiency as compared with the DC prediction coding, wherein among the coefficients of a prediction block, not only the DC coefficient but also the AC coefficient is predicted. For example, when block C is selected as prediction block P, all of the coefficients at the upper edge of block C are the subject of prediction. When block A is selected as prediction block P, all of the coefficients at the left edge of block A are the subject of prediction. The read scan mode in the coding process is the alternate horizontal scan (third scan) when block C is selected as prediction block P. When block A is selected as prediction block P, the read scan mode is the alternate vertical scan (fourth scan). That is, the read scan mode in the coding process changes according to selected prediction block P.
The DC prediction coding and the DC/AC predictive coding are adaptively switched. For example, when it is determined that the DC/AC predictive coding achieves higher coding efficiency than the DC prediction coding, the DC/AC predictive coding is employed; but when otherwise, the DC prediction coding is employed. Thus, in MPEG-4, the read scan mode in the coding process needs to support three read scan modes, e.g., alternate horizontal scan, alternate vertical scan, and zigzag scan, rather than only one read scan mode as in JPEG, or the like. In the case where the coding process is performed by using only the DC prediction, the read scan is fixed to the zigzag scan, and therefore, parallel reading of coefficients can be achieved using the technique described in the above-mentioned publication. However, in the case where the coding process is performed by using the DC/AC prediction, the read scan mode is not determined among the three read scan modes till writing of DCT coefficients in that block (determination of AC prediction effect) is completed. Therefore, when n DCT coefficients which are consecutive in the write scan order are sorted into n memories, n consecutive coefficients need to be read in parallel in the selected read scan order no matter which read scan mode is selected.
FIGS. 28A to 28D show specific examples of a coding process that requires a plurality of such read scan modes wherein the technique disclosed in the above-mentioned publication is applied. FIG. 28A shows the first scan (raster scan) which corresponds to FIG. 24A. FIG. 28B shows the second scan (zigzag scan) which corresponds to FIG. 24B. FIG. 28C shows the third scan (alternate horizontal scan). FIG. 28D shows the fourth scan (alternate vertical scan).
As clearly seen from FIGS. 28B to 28D, it is difficult to simultaneously read n consecutive coefficients in the read scan order from n different memories that constitute the storage unit (herein, n=2) for all of the three read scan modes. For example, in the third scan shown in FIG. 28C, coefficients 2 and 3 and coefficients 6 and 7 have to be read from the second memory 702. However, it is impossible to read two coefficients in parallel at one time because these coefficients are stored at different addresses. In this read scan mode, coefficients 16 and 17 and coefficients 10 and 11 have to be read from the first memory 701. However, it is impossible to read two coefficients in parallel at one time because these coefficients are stored at different addresses.
The example described herein is merely an example of memory division wherein the storage unit is formed by two memories in the process of reading two coefficients in parallel. It is difficult to solve the above problems no matter how two coefficients are allocated to two memories.